Native CPU Runtime Migration Plan

Scope: EvoSpikeNet-Core
Status: Design plan for future implementation
Assumption: CPU production inference is the primary target; research, GPU, and external-model paths remain available during migration
Updated: 2026-09-14

Purpose

The migration covers the complete inference path, not only sigmoid: Torch, SNN, Transformer, quantization, sparse structures, and model artifacts. The long-term goal is to run production inference through a NativeCPUBackend.

Existing libraries must not be removed immediately. Keep the Torch backend and Native CPU backend in parallel, and switch each component only after numerical, performance, and artifact compatibility are verified.

Current INT16 sigmoid

ChronoSpikeAttention supports activation_type="int16". It uses Q8.8 inputs and a Q0.15 LUT approximation, while preserving the existing float [0, 1] output contract.

This is currently a Torch-tensor compatibility implementation, not a native CPU implementation. The native version should move the same contract to a C++ or Rust CPU kernel.

CPU benchmark

Store the CPU baseline in EvoSpikeNet-Core/benchmarks/results/sigmoid_precision_cpu.json. Re-run it with:

cd EvoSpikeNet-Core
PYTHONPATH=. python3 benchmarks/sigmoid_precision_bench.py \
  --device cpu \
  --elements 1000000 \
  --warmup 10 \
  --runs 30 \
  --output benchmarks/results/sigmoid_precision_cpu.json

Measure:

latency for FP32, INT8 Q0.7, and INT16 Q0.15
MAE, RMSE, and maximum absolute error
agreement at the 0.5 threshold
output saturation rate

Do not judge native migration from the Torch LUT speed alone. Compare Linear, SNN, sparse synapses, attention, and end-to-end inference with identical inputs, weights, and seeds.

Migration scope

Native core

tensor shape, dtype, and layout
add, multiply, reduction, clamp, and compare
matmul, gather, and scatter
Q8.8 / Q0.15 fixed-point arithmetic
sigmoid, ReLU, and tanh
LIF, Izhikevich, EvoLIF, membrane state, and reset
COO/CSR sparse synapses and delay buffers
ChronoSpikeAttention and the required Transformer inference blocks
native model artifact loader

Keep initially

Hugging Face tokenizers and pretrained models
ONNX Runtime, FAISS, and scikit-learn
FastAPI / Uvicorn
Qiskit
CUDA / TensorRT / Edge TPU-specific paths
training autograd, optimizers, and existing .pt / .pth loading

Staged rollout

Specify shapes, dtypes, spike ranges, sparse index rules, RNG, and artifact schema.
Compare CPU scalar kernels with the Torch golden reference.
Port INT16 sigmoid, ReLU, clamp, reduction, and matmul.
Port LIF, membrane state, sparse synapses, and delay buffers.
Port inference-only attention and required Transformer blocks.
Connect the native artifact loader and runtime adapter.
Enable the feature flag per model and fall back to the Torch backend on failure.
Consider autograd, training, and distributed synchronization only if CPU production requires them.

Production gates

Enable the Native CPU backend only for models meeting at least these conditions:

FP32 output cosine similarity >= 0.999
sigmoid threshold agreement >= 99.9%
spike count agreement >= 99.9%
p95 latency <= current production path
24-hour soak with no unbounded memory growth
existing checkpoint load succeeds

Flight-safety certification, Safety Barriers, and sensor product specifications are outside this plan and require separate validation by the consuming system.